1) Field of the Invention
The present invention relates to technology for power source control of an expanded apparatus (subsidiary apparatus) connected to a central apparatus (main apparatus).
2) Description of the Related Art
In a previous power source control system 100, as shown in FIG. 9, for example, a central power source control unit 112 for performing power source control of power source units 111a through 111c of a central apparatus (main apparatus; for example, main server) 110 and expanded power source control units 122 for performing power source control of power source unit 121-1 through 121-n of multiple (n-number of; here, n is an integer greater than 1) expanded apparatus (subsidiary apparatus; for example, expanded server apparatus) 120-1 through 120-n connected to the central apparatus 110 are connected through buses 130. The central power source control unit 112 determines power source control content of the power source units 121-1 through 121-n of the expanded apparatus 120-1 through 120-n, and the power source control content is transmitted to the expanded power source control units 122 through the buses 130.
Further, the power source units 121-1 through 121-n are three power source units 121a through 121c. 
Each of the power source units 111a through 111c supply electric power to, for example, the CPU (Central Processing Unit; not illustrated) or a storage device (not illustrated) of the central apparatus 110. In addition, the power source units 121a through 121c supply electric power to the CPU (Central Processing Unit; not illustrated) or a storage device (not illustrated) of the central apparatus 120.
The central power source control unit 112 includes: a computing unit [for example, MPU (Micro Processing Unit)] 113 which computes power source control information as the control content (for example, power ON or OFF) of the power source unit 111a through 111c and power source control information as the control content of the power source unit 121-1 through 121-n; a central power source control register 114 which holds power source control information of the power source units 111a through 111c and controls the power source units 111a through 111c on the basis of the power source control information; and a central side expanded power source control unit 115 including an interface control unit 115a which transmits power source control information of the power source unit 121-1 through 121-n computed by the computing unit 113 to the corresponding expanded power source control unit 122 through the bus 130.
In this instance, the central power source control register 114 has an output register 114a which holds power source control information for the power source units 111a through 111c computed by the computing unit 113 and a reading register 114b which holds power source information (for example, an alarm signal) from the power source units 111a through 111c. 
The reading register 114b further includes: a direct reading register 114c which is a register that directly reads signal and holds power source information from the power source units 111a through 111c; a rising edge/falling edge flag register 114d which performs noise absorption sampling for each bit of the direct reading register 114c and holds the result of the detected rising edge/falling edge; an interrupt mask register 114e which sets whether or not an interrupt signal is to be transmitted to the computing unit 113 upon reception of power source information from the power source units 111a through 111c; a rising edge/falling edge detecting register 114f which sets at which of rising edge or falling edge, the presence or absence of an alarm signal from the power source units 111a through 111c is to be detected; a sampling cycle register 114g which holds detection cycle (for example, successive detection time of alarm signals which is required to decide that an alarm signal is detected) for absorbing noise of an alarm signal from the power source units 111a through 111c. 
In this instance, rising edge/falling edge flag register 114d can be cleared by the computing unit 113, and sampling cycle for noise absorption is set by the sampling cycle register 114g, and further, effective/non-effective setting can be performed by the rising edge/falling edge detecting register 114f. 
For example, when the sampling cycle set in the sampling cycle register 114g is 32 ms, and the rising detection register 114f is effective (falling edge detection register 114f is ineffective), and an alarm signal from the power source units 111a through 111c is positive (+), if the high level of an alarm signal successively appears not shorter than 32 ms, the rising edge flag register 114d turns ON, and an interrupt occurs in the computing unit 113.
After log collection, that is, after confirming an error factor, the computing unit 113 clears the rising edge flag register 114d, and makes the rising edge detecting register 114f ineffective, and makes the falling edge detecting register 114f effective.
If a predetermined time (32 ms) is elapsed after an alarm signal becomes low level, the falling edge flag register 114d turns ON, and an interruption occurs in the computing unit 113. The computing unit 113 confirms that an alarm is vanished, and clears the falling edge flag register 114d to make the falling detection register 114f ineffective, and makes the rising edge detecting register 114f effective to monitor an alarm.
In this instance, log (alarm details) collection by the computing unit 113 is realized by reading information in the direct reading register 114c and the rising edge/falling edge register 114d. 
Further, the expanded power source control units 122 of each of the expanded apparatus 120-1 through 120-n includes: an interface control unit 123 which receives power source control information sent from the interface control unit 115a of the central power source control unit 112 via the bus 130; and an expanded power source control register 124 which performs power source control of the power source unit 121-1 through 121-n on the basis the power source control information received by the interface control unit 123.
In this instance, as in the case of the central power source control register 114, the expanded power source control register 124 also includes: an output register 124a and a reading register 124b (that is, direct reading register 124c, rising edge/falling edge flag register 124d, interrupt mask register 124e, rising edge/falling edge detecting register 124f, and sampling cycle register 124g) corresponding to the output register 114a and the reading register 114b (that is, direct reading register 114c, rising edge/falling edge flag register 114d, interrupt mask register 114e, rising edge/falling edge detecting register 114f, and sampling cycle register 114g), respectively.
Further, in FIG. 9, an output register 124a and a reading register 124b of the expanded power source control register 124 of the expanded apparatus 120-n are not illustrated for simplification of the drawing.
Here, the interface control unit 115a of the central power source control unit 112 and the interface control unit 123 of the expanded power source control unit 122 perform data transceiving therebetween with the parallel bus scheme (parallel transfer scheme). Accordingly, the bus 130 is a parallel bus composed of multiple signal lines.
Then, in the power source control system 100, the computing unit 113 computes power source control information for instructing ON/OFF of power source and writes it in the output register 114a of the central power source control register 114. As a result, power source of the central apparatus 110 is turned ON or OFF.
In this instance, the central power source control unit 112 performs power source control of the power source unit 111a through 111c under the state that the central apparatus 110 is powered off (that is the central apparatus 110 is not supplied with electric power from the electric power unit 111a through 111c). Regardless of the power state of the central apparatus 110, the central power source control unit 112 is an always powered-on control unit which is always operable with supply of electric power from the power source units 111a through 111c or another power source.
Turning ON or OFF of the expanded apparatus 120-1 is realized by the computing unit 113 which computes power source control information to the power source unit 121-1 and writes in an output register 124a of the corresponding expanded power source control register 124. That is, the central side expanded power source control unit 115 transmits such power source control information to the expanded power source control unit 122 of the expanded apparatus 120-1, and the expanded power source control unit 122 performs power source control of the power source unit 121-1 on the basis of such power source control information.
In this instance, as in the case of the central power source control unit 112, the expanded power source control unit 122 is supplied with power from power source units 121-1 through 121-n (hereinafter, power source units 121-1 through 121-n are simply indicated by the reference character 121 when they are not particularly distinguished thereamong) or from another power source, and thus, the power of the expanded power source control unit 122 is always ON, independently from the power source state of the expanded apparatus 120-1 through 120-n.
Power source state monitoring of the expanded apparatus 120-1 through 120-n is performed by the computing unit 113 which reads the output register 124a of the expanded power source control register 124 of the expanded apparatus 120-1 through 120-n through the interface control unit 123 and the interface control unit 115a (central side expanded power source control unit 115) through the bus 130, or by the expanded power source control unit 124 of the expanded apparatus 120-1 through 120-n which samples an alarm signal from the power source unit 121-1 through 121-n with the reading register 124b, and sends an interrupt (in the drawing, described as “the control signal (interrupt)” and “an interrupt signal”) to the computing unit 113 (in the drawing, see arrow 131-1, 131-n, and 116).
Upon receipt of an interrupt signal from the expanded power source control unit 122, the computing unit 113 reads alarm details from the power source unit 121 held in the direct reading register 124c in the reading register 124b of the expanded power source control register 124 of the expanded power source control unit 122 by way of the bus 130, thereby understanding power source state of the expanded apparatus 120-1 through 120-n.
In the parallel bus scheme, an address path and a data path are common. After an address is set with an address strove signal, data is transmitted. The bus 130 is composed of multiple signal lines for transceiving eight bits and one parity bit, and eight signal lines (see arrow 131-1, 131-n, 132-1, 132-n) for other control signals (interrupt signal, read/write signal, address strove signal, DATA-ACKNOWLEDGE signal, etc.).
Further, the interface control unit 115a and each interface control unit 123 control bus timing of the bus 130.
In this instance, in a previous art, a controller (power source control device) for controlling power source and at least one power source are used for transmitting power source control information (signal) with serial line communication (serial data bus scheme) (see the following patent documents 1 and 2). In another previous art, power source control of an expanded box connected to a personal computer through a docking base and power source control of such docking base are performed by the CPU of the personal computer on the basis of a processing routine for performing power source control held in a BIOS-ROM (Basic Input/Output System-Read Only Memory) (see the following patent document 3).
Here, according to the power source control system 100 of FIG. 9, in access from the computing unit 113 to the output register 124a of the expanded power source control register 124 of the expanded power source control unit 122, when the interface control unit 123 of the expanded power source control unit 122 receives power source control information sent from the computing unit 113, it returns DATA-ACKNOWLEDGE signal (in the drawing, described as “ACK signal”, and the computing unit 113 receives this DATA-ACKNOWLEDGE signal, the access being thereby completed (see arrow 117). Accordingly, the access from the computing unit 113 to the output register 124a of the expanded power source control register 124 of the expanded power source control unit 122 is performed by way of the bus 130, and the DATA-ACKNOWLEDGE signal needs to be received by way of the bus 130, so that access time is increased.
Further, once the computing unit 113 starts accessing to the output register 124a via the central side expanded power source control unit 115, it cannot perform any other processing until the access is completed by reception of a DATA-ACKNOWLEDGE signal from the expanded power source control unit 122. Thus, longer access time results in lower processing speed of the computing unit 113.
Likewise, in access from the computing unit 113 to the reading register 124b of the expanded power source control register 124 of the expanded power source control unit 122, data need to be transceived by way of the bus 130, resulting in longer access time.
That is, the reading register 124b of the expanded power source control register 124 on the expanded apparatus 120-1 side has a setting function for alarm monitoring [that is, interrupt mask register 124e, rising edge/falling edge detecting register 124f, sampling cycle (monitoring time setting; sampling adjusting) register 124f] and an alarm monitoring function. Thus, when an alarm occurs in the power source units 121-1 through 121-n, it is necessary for the computing unit 113 to access the reading register 124b of the expanded power source control register 124 on the expanded apparatus 120-1 through 120-n, so that time required for collecting a log or the like relating to an alarm is lengthened.
During such access being performed, the computing unit 113 cannot perform any other processing, so that longer access time to the reading register 124b causes the processing speed of the computing unit 113 reduced.
Further, in the previous power source control system 100, since the central power source control unit 112 and the expanded power source control unit 122 are connected by a parallel bus interface. Thus, the number of signal lines of the bus 130 is large. A larger number of expanded devices 120-1 through 120-n cause a significantly large number of signal lines of the bus 130, so that it becomes complicated to manage and organize signal lines between the central power source control unit 112 and the expanded power source control unit 122.
[Patent document 1] Japanese Patent Laid-open No. 2003-271018
[Patent document 2] Japanese Patent Public Notification No. HEI 8-23792
[Patent document 3] Japanese Patent Laid-open No. 2001-84064